In many semiconductor device structures, it is desirable to provide a doped semiconductor region of small dimension and well-controlled doping concentration. In a typical high-performance, vertical bipolar transistor, for example, it is desirable to provide an intrinsic base region of very shallow dimension, i.e. on the order of 50-100 nanometers (mm), and possessed of a well-controlled doping concentration.
Several methods are currently known for providing such small-dimensioned, well-controlled doped regions. Ion implantation, a process well understood in the art, is one method of forming a shallow doped region in a semiconductor substrate. Ion implantation, however, suffers from the disadvantage of channeling effects when used to implant boron to form the very thin regions of the type described herein.
Solid phase diffusion from polysilicon is another method of forming a very thin doped region. See, for example, U.S. Pat. No. 4,431,460 to Barson et al. (assigned to the assignee of the present invention), wherein various regions of a semiconductor device are out-diffused into a silicon substrate from a doped polysilicon layer. Such solid phase diffusion from polysilicon, however, can result in the uneven distribution of dopant atoms at the grain boundaries within the polysilicon, and at the polycrystalline-single crystal boundary between the polysilicon and the underlying silicon substrate.
Sugiyama, M., et al., "A 40 GHz f.sub.t Si Bipolar Transistor LSI Technology," IEDM-89, pgs. 221-224, shows a vertical bipolar transistor wherein a shallow base region is formed by solid phase out-diffusion from boro-silicate glass (BSG). The BSG is then removed to accommodate the formation of an emitter. BSG, however, is not a good diffusion source in that it is very difficult to control the dopant concentration provided therefrom. Further, like polysilicon, because the crystalline structure of BSG is different from that of silicon, an undesirable accumulation of dopant atoms occurs at the interface between the two materials.
Meyerson, B. S., "Low-Temperature Silicon Epitaxy by Ultrahigh Vacuum/Chemical Vapor Deposition," Appl. Phys. Lett. 48(12), 1986, pp. 797-799, shows a method of forming, at a low temperature and in a high vacuum, very thin layers of epitaxial silicon. These layers can be formed in situ doped to a very tightly controlled doping concentration. The teachings of Meyerson represent a recent and substantial contribution to the art. In fact, many device structures are currently known which incorporate the use of low temperature epitaxial (LTE) layers of the type taught by Meyerson.
The present inventors have determined, however, that it is not always desirable to retain the Meyerson LTE layer within a completed semiconductor device structure. Such LTE layers may, for example, exhibit crystalline defects not present in the underlying silicon, rendering the devices with undesirable transistor characteristics. The present inventors have further recognized the desirability of utilizing the well-controlled doping characteristics otherwise provided by a Meyerson LTE layer.